Many electronic systems utilize high voltage signals that exceed the 5V or less logic signal levels of typical digital systems. For example, applications such as communications systems that incorporate modems, serial line drivers, etc., may be required to operate at elevated voltage levels. In many flat panel displays, row and column electrodes are driven by low cost integrated circuits (`ICs`) that must be capable of driving high voltages. Many types of nonvolatile semiconductor memories, e.g. EPROMs, EEPROMs and flash EEPROMs, require on-chip manipulation of high voltage signals in order to control programming. Implantable electronic medical devices, such as pacemakers, often require signal or output voltages in the range of 5V to 40V.
Conventional monolithic high voltage amplifier circuits have been fabricated in special Complimentary Metal-Oxide Semiconductor ("CMOS") processes that permit high voltage operation, since transistors fabricated in conventional low voltage CMOS processes typically break down at voltages around 6V to 10V. Transistor breakdown is due to phenomenon such as zener breakdown of the drain, short channel effects and gate oxide failure. J. Y. Chen, CMOS Devices and Technology for VLSI, Prentice Hall, Englewood Cliffs, N.J., 1990; S. M. Sze, Semiconductor Devices Physics and Technology, John Wiley & Sons, New York, 1985. Double diffused drain structures, thicker oxides and long channel Field Effect Transistors ("FETs") have been used in high voltage processes to achieve higher voltage break down levels. But these modifications result in characteristically larger transistors, i.e. a minimum transistor length greater than about 1.5 .mu.m as compared to less than 0.5 .mu.m for low voltage transistors. Larger transistors limit the integration density of the transistors.
Integrated circuits are generally fabricated with standard (also known in the art as "commodity") CMOS processes that are less expensive than specialty high voltage CMOS processes, but are only capable of reliably supporting voltages at or below 5 volts. Combining large, high voltage transistors with small, low voltage transistors on the same semiconductor substrate can be relatively expensive as a result of additional mask steps in the IC fabrication process. Therefore, specialty fabrication of conventional high voltage circuits raises the cost of manufacturing for applications that require extended voltage ranges.
Integrated circuits that implement high voltage circuitry using a low voltage fabrication process have been reported, but with limited applicability. In these circuits, high voltage n-Field Effect Transistors ("n-FETs") and p-FETs are fabricated by extending the drain terminal of the FETs with lightly doped parasitic implants. See Z. Parpia, C.A.T. Salama and R. A. Hardaway, `Modeling and Characterization of CMOS-Compatible High-Voltage Device Structures,` IEEE Transactions on Electron Devices, Vol. ED-34, No. 11, 1987, pp. 2335-2343; M. J. Declercq, M. Schubert and F. Clement, `5V-to-75V CMOS Output Interface Circuits,` Proceedings of the International Solid State Circuits Conference, San Francisco, 1993, pp. 162-163. These high voltage FETs have lightly doped drain-to-substrate diodes which diodes for standard CMOS fabrication processes typically can sustain voltages of over 40V. These high voltage n-FETs and p-FETs can be used in operational amplifiers and buffer circuits with conventional transistor arrangements.
One of the problems the devices described by Parpia et al. and Declercq et al. have is that the gate oxide between the low voltage gate and the high voltage drain is a thin oxide, which cannot reliably withstand voltages above 5V for most small geometry CMOS processes. Fabricating high voltage devices using small device geometries (i.e. sub micron transistor length) can degrade the transistor significantly and impact long term reliability, if the transistors must sustain voltages above 5V. This degradation is due to the phenomenon of electron tunneling, avalanche breakdown and charge retention in oxide traps. For this reason, previously described high voltage circuits have been restricted to relatively large geometry (i.e. greater than 1.5 .mu.m minimum transistor length) low voltage CMOS processes, a restriction that hinders the integration density and hence applicability of the circuits.
Another problem with the previously described devices is the large gate-to-drain capacitance caused by the overlap of the drain and gate regions. Since the lightly doped parasitic implants are not self-aligned with the gate, as is the case with conventionally fabricated transistors, the overlap and hence capacitance of these transistors can be significantly larger than that of self-aligned transistors. These large capacitances can significantly limit the speed of the transistors.
For applications in which power consumption is a concern, such as battery-powered devices, amplifiers that minimize power-supply currents and have low power-supply voltage operation are desirable. Examples of conventional micropower operational amplifier designs are described in P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Holt, Rinehart and Winston, New York, 1987, pp. 497-504. Traditionally, such micropower amplifier designs were unable to provide large output currents while still maintaining micropower consumption when quiescent. A dynamically or adaptively-biased operational amplifier has been described that attempts to overcome this problem by boosting the tail current when a differential input is applied. Degrauwe, et al, `Adaptive Biasing CMOS Amplifiers,` IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 3, June 1982, pp. 522. However, the solution presented by Degrauwe et al suffers from instability problems and requires well-matched components.